| Digital and Mixed Signal Design |
| IO and ESD Design |
| Padring Design including Power Cells |
| Full Digital and Analog PLL |
| Specialized IO Cells like USB, I2C, I2S, LVDS, PCIX and others |
| Synopsis Design Compiler and Logic Synthesis Tool |
| SCAN Test hardware schemes |
| JTAGdesign |
| Static and Dynamic timing analysis like Primetime, Timemill, pathmill and others. Power analysis tool like spice and Powermill. |
| Familiarity with Hspice, Smartspice, Pspice., Mcspice, Mtime. |
| HDL languages: Verilog, VHDL, N.2 |
| Cadence, Mentor Graphics, and Silvaco schematic entry tools |
| Various new and old Layout tools |
